Verilog Hardware Description Language (HDL)

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Verilog Hardware Description Language (HDL)Why Use a HDL Easy way to describe complex digital designs.Describe digital designs at a very high level of abstraction (behavioral) and a very lowlevel of abstraction (netlist of standard cells).Simulate digital designs using Modelsim, Verilog-XL, etc.Synthesize digital designs using Synplicity, XST (Xilinx ISE), Ambit, Synopsys,Leonardo, etc.Simulate post synthesis netlist to verify timing.Verilog vs. VHDL Both designed for simulation not synthesisVerilog uses C like syntax – very concise. VHDL is strongly typed.Verilog: “Most widely used Hardware Description Language in the U.S.” (someone atHarvard but the web page was moved).“In the United States, the commercial industries tend to use more Verilog, while theaerospace and defense industries more heavily favor -vs-vhdl)IMO, Verilog is easier to learn/use than VHDL.Z:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 1 of 16

4 Levels of Abstraction Behavioral1. Describe the algorithm without concern for the actual logic required to implementit.2. For example, a Behavioral description for an 8 bit, 2 input multiplexer is shownbelow in bold:// Mux2To1.v// Behavioral description of 2 input multiplexer with// parameter Width resetall timescale 1ns/10psmodule Mux2To1(A0,A1,Y,Sel);parameter Width 8;input [Width-1:0] A0, A1;output [Width-1:0] Y;inputSel;wire [Width-1:0] A0, A1;reg [Width-1:0] Y;wire Sel;always @ *begincase (Sel)0: Y A0 ;default: Y A1 e1\Verilog HDL Introduction.docPage 2 of 16

3. What’s all this: // - comment character resetall - resets all compiler directives to default values. Note that this is (underneath the ) and not ‘ underneath the “. timescale 1ns / 10ps - specifies time unit/precision – Important in yourTestbenches when you want to wait 20 ns before changing the stimulus. Create Verilog component with a module statement.1. parameter is used to set constants in Verilog just like the #defineis used in C. However, the parameter can be overridden duringinstantiation. This way, Mux2To1 can be used for any size vectors.2. Bus size is indicated using [].3. Specify direction of ports with input, output or inout.4. Declare ports and other signals:o wire or reg - Assumes 1 bit wire if you don’t specify. case statement used to describe Mux. Blocks of code are grouped together using begin/end like you use {} in C. More about always, wire and reg later. Dataflow1. Describe the algorithm in terms of logical data flow.2. For example, the Dataflow description for an 1 bit, 2 input multiplexer is shownbelow in bold:// Mux2To1DFlow.v// Dataflow description of 1 bit, 2 input multiplexor resetall timescale 1ns/10psmodule Mux2To1DFlow(A0,A1,Y,Sel);inputoutputinputA0, A1;Y;Sel;wire A0, A1, Y;wire Sel;assign Y (A1 & Sel) (A0 & !Sel) ;endmodule3. Some Verilog operators: & - bitwise And && - logical And - bitwise Or - Logical Or4. Verilog code that combines Dataflow and Behavioral coding styles is commonlyreferred to as RTL (Register Transfer Language). Gate LevelZ:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 3 of 16

1. Describe design in a Netlist of the actual logic gates and the interconnectionbetween them. This is usually generated from the RTL by the Synthesis tool.2. For example:mx21 I0 I0 U599 (.Q(I0 I0 n602),.I0(\I0 I0 I20 I23 QB[0] ),.I1(I0 I0 n 296721027),.S(I0 I0 I20 I23 I0 n 20431));df202 I0 I0 I20 I23 I8 q reg 1 (.Q(\I0 I0 I20 I23 QB[1]),.C(I0 I0 CLK0),.D(I0 I0 n603),.SD(\I0 I0 I20 I23 QB[0] ),.SE(n 624));mx21 I0 I0 U600 (.Q(I0 I0 n603),.I0(\I0 I0 I20 I23 QB[1] ),.I1(I0 I0 I20 I23 I8 n 20536),.S(I0 I0 I20 I23 I0 n 20431));df202 I0 I0 I20 I23 I8 q reg 2 (.Q(\I0 I0 I20 I23 QB[2]),.C(I0 I0 CLK0),.D(I0 I0 n604),.SD(\I0 I0 I20 I23 QB[1] ),.SE(n 624)); From Cadence’s synthesis tool AMBIT targeting AMI 0.5um standard celllibraryInstantiation of 2 - mx21’s and 2 - df202’sPorts connected by name here.1. mx21 has 4 ports: Q, I0, I1 and S.2. I0 I0 U599 is the name of an instance of a mx21.o I0 I0 n602 is a wire connected to the Q input.You can also connect without the name if you go in order.Switch Levelpmos (C,Pwr,B) ;pmos (Out,C,A) ;nmos(Out,Gnd,A) ;nmos(Out,Gnd,B) ;1. For example, what circuit is described above? Format: 1\Verilog HDL Introduction.docPage 4 of 16

2. Describe design in a Netlist of switches (FETs), and the interconnect betweenthem.3. Description of a 2 input Nor gate is shown below:Figure 1. Nor Gate from Palnitkar, p. 221.// Nor2Switch.vmodule Nor2Switch(A,B, Out) ;input A, B ;output Out ;wire C ;supply1 Pwr ;supply0 Gnd ;// Instantiate FETs: pmos(source,drain,gate) or nmos(drain,source,gate)pmos (C,Pwr,B) ;pmos (Out,C,A) ;nmos(Out,Gnd,A) ;nmos(Out,Gnd,B) ;endmoduleZ:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 5 of 16

Structural Verilog Structural Verilog modules are used to instantiate and connect other Verilog modulestogether.Consider the 8 bit, 3 input multiplexer is shown below:// Mux3To1// Structural HDL implementation of 3 input, 10 bit mux using 2 Mux2To1’s// parameterized by Width resetall timescale 1ns/10psmodule Mux3To1( A0, A1, A2, Sel, Y);parameter Width 10;input [Width-1:0] A0, A1, A2;input [1:0] Sel;output [Width-1:0] Y;wire [Width-1:0]wire [1:0] Sel;A0, A1, A2, Y, YInt ;Mux2To1 #(Width) U 0( .A0 (YInt), .A1 (A2), .YMux2To1 #(Width) U 1(A0,A1,YInt,Sel[0:0]);(Y), .Sel (Sel[1:1]));endmodule // Mux3To1 2 instances of Mux2To1, U 0 and U 1.You can either connect ports by name (U 0) or by declaration order (U 1).The #(Width) is used to override the default value of 8 in the Mux2To1 module to createa 10 input mux. This could be still be overridden when you instantiate Mux3To1. wire YInt connects the output of instance U 1 to the A0 input of U 0. What happens if Sel 2' b11?Z:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 6 of 16

Combination Logic in Verilog 2 ways to create Combinational Logico Use assign statement shown above in Mux2To1DFlow.v Operators in Verilog (shown below) are similar to C.Figure 2: Verilog Operators from Palnitkar, p. 92. For example:o Behavioral description of Full Adderoassign {COut,Sum} a b CIn ;Z:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 7 of 16

o Dataflow description of Full AdderooCinassign Sum CIn A B ;assign COut (A&B) (CIn & (A B)) o assign QOut 8' b1010101;o assign QOut ' ha0;o Use an always block If then else and case statements only allowed in an always block. Outputs must be type reg. Follow these simple rules to avoid inferring a latch (very bad!):o The Sensitivity List is @ *.o Assign ALL outputs (LHS of ) under ALL conditionso case statements cover all possible cases of the condition orhave a default case.o if/then/else statements cover all possible cases of thecondition or have an else condition.OR o All outputs are assigned a default value at the top of thealways block. Then, override the defaults as needed withcase or if/then/else statements.o Use for assignments. (Blocking)o “Left Hand Side” of are the outputs from this alwaysblock (end in D).o “Right Hand Side” of are the inputs to this always blockwhich should be flop outputs (or module inputs or RAMoutputs).See Mux2To1.v example above.Z:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 8 of 16

Another behavioral always block for Mux2To1always @ *beginY A0 ;if (Sel 1)Y A1 ;endZ:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 9 of 16

Sequential Logic in Verilog Always needs an always block.Use for all assignments. (Non-Blocking)Outputs must be type reg., Inputs may be of type wire or reg.Sensitivity list should only have posedge Clk or negedge Clk.o You won’t need asynchronous resets in this class (i.e., posedge Reset)o Don’t gate clock! Use only Clk to clock your flops.For example, the RTL for a D-Flip Flop is shown below:// DReg.v// Register - Reset to 0, Latches on LE resetall timescale 1ns/10psmodule DReg(D, LE, Reset, Clk, Q);parameter Width 8;input [Width-1:0] D;input LE, Reset, Clk;output [Width-1:0] Q;wire [Width-1:0] D;wire LE, Reset, Clk;reg [Width-1:0] Q;always @ (posedge Clk)beginif (Reset)Q 0 ; // Reset Qelse if (LE)Q D log HDL Introduction.docPage 10 of 16

o RTL for an up/down counter is shown below:// CntrUpDown.v EJR 11/26/05// Up-Down Counter with latch enable and count enable.// Loads Counter with D when LE asserted// Count Up (Up 1) or Down (Up 0) when CE asserted resetall timescale 1ns/10psmodule CntrUpDown(D, LE, CE, Up, Reset, Clk, Count);parameter Width 8;input [Width-1:0] D;input LE, CE, Up, Reset, Clk;output [Width-1:0] Count;wire [Width-1:0] D;wire LE, CE, Up, Reset, Clk;reg [Width-1:0] Count ;reg [Width-1:0] CountD ;// Combinational Block for CountDalways @ *beginCountD Count ;if (LE)CountD D ;else if (CE)CountD Up ? Count 1 : Count - 1 ;end// Sequential Block for Countalways @ (posedge Clk)beginif (Reset)Count 0 ; // Reset CountelseCount CountD log HDL Introduction.docPage 11 of 16

o RTL for a shift register:// ShiftReg.v// Shift Register - shifts ShiftIn into the MSB of Q. resetall timescale 1ns/10psmodule ShiftReg(ShiftIn, LE, Reset, Clk, Q) ;parameter Width 8 ;input ShiftIn, LE, Reset, Clk ;output [Width-1:0] Q ;reg [Width-1:0] Q ;wire [Width-1:0] D {ShiftIn,Q[Width-1:1]} ;always @ (posedge Clk)beginif (Reset)Q 0 ; // Reset Qelse if (LE)Q D ; // Concatenate ShiftIn and Q log HDL Introduction.docPage 12 of 16

wire vs. reg reg is for outputs of always or initial blocks.wire is for everything else.Use reg signed or wire signed with 2s complement operations like signed comparisons( , ).Verilog Naming Rules Case SensitiveNames must begin with alpha character No special characters in a name exceptTestbenches in Verilog Generate stimulus to test your design. View the response to the stimulus in the simulator.Never gets synthesized – only used for test.Instantiate DUT (Device Under Test) and drive it with your testbench.Use the following Verilog constructso initial block – execute at the beginning of the simulation Use for assignment (Blocking). Outputs are type reg.o always block Use for assignment (Blocking). Outputs are type reg.o integer (32 bit) and real (64 bit IEEE double precision) data types available.o Use for and while loops inside always and initial blocks. For example:integer i ;initialbeginfor (i 0;i 10;i i 1)begin// Verilog code hereEndi 0 ;while (i 10)begin// Verilog code herei ;endendo The delay operator # - Use in an assignment statement or on a line by itself topace the stimulus.o display task – Use this to print results to the simulator console. Uses sameformat as printf.o readmemh task – Reads an ascii file of hexadecimal values into a reg array.Z:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 13 of 16

o stop task – Use this to stop the simulation when stimulus is complete.For example, the testbench, CntrUpDown tb.v for CntrUpDown is shown below:Verilog ReferencesZ:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 14 of 16

CntrUpDown Example of an Inferred Latch (VerilogExamples) Simulate CntrUpDown tbSynthesize CntrUpDownRemove default assignment (line 24)SimulateSynthesize (look at warnings)//CntrUpDown tb.v resetall timescale 1ns/10psmodule CntrUpDown tb() ;parameter Width 16 ;integer i ;reg [Width-1:0] D ;reg LE, CE, Up, Reset, Clk ;wire [Width-1:0] Q ;CntrUpDown #(Width) CntrUpDown1(D, LE, CE, Up, Reset, Clk, Q);initialbeginD 0 ; LE 0 ; CE 0 ; Up 0 ; Reset 1 ; Clk 0 ;#8 ;Reset 0 ; LE 1 ; D 1000 ;#10 ;LE 0 ;for (i 0;i 16;i i 1)beginCE 1 ;#10 ;CE 0 ;#10 ;endUp 1 ;for (i 0;i 16;i i 1)beginCE 1 ;#10 ;CE 0 ;#10 ;end stop ;endalwaysbegin#5 Clk Clk log HDL Introduction.docPage 15 of 16

Modelsim results for CntrUpDown tb:Z:\Home\cse465\Lectures\Lecture1\Verilog HDL Introduction.docPage 16 of 16