PACT HDL: A C Compiler Targeting ASICs And FPGAs With .

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PACT HDL: A C Compiler Targeting ASICs and FPGAs withPower and Performance Optimizations*Alex Jones Debabrata Bagchi Satrajit Pal Xiaoyong Tang Alok Choudhary Prith BanerjeeCenter for Parallel and Distributed ComputingDepartment of Electrical and Computer EngineeringTechnological Institute, Northwestern University2145 Sheridan Road, Evanston, IL 60208-3118Phone: (847) 491-3641 Fax: (847) 491-4455Email: {akjones, bagchi, satrajit, tang, choudhar, banerjee}@ece.northwestern.eduABSTRACT1. INTRODUCTIONChip fabrication technology continues to plunge deeper into submicron levels requiring hardware designers to utilize everincreasing amounts of logic and shorten design time. Toward thatend, high-level languages such as C/C are becoming popularfor hardware description and synthesis in order to more quicklyleverage complex algorithms.Similarly, as logic densityincreases due to technology, power dissipation becomes aprogressively more important metric of hardware design. PACTHDL, a C to HDL compiler, merges automated hardwaresynthesis of high-level algorithms with power and performanceoptimizations and targets arbitrary hardware architectures,particularly in a System on a Chip (SoC) setting that incorporatesreprogrammable and application-specific hardware. PACT HDLis intended for applications well suited to custom hardwareimplementation such as image and signal processing codes. Bymaking the compiler modular and flexible, optimizations may beexecuted in any order and at different levels in the compilationprocess. PACT HDL generates industry standard HDL codes,such as RTL Verilog and VHDL, which may be synthesized andprofiled for power using commercial tools. This is the first paperon the PACT compiler project in a series. The compilerframework and introductory optimizations are presented. Laterpapers will focus on these and other optimizations in detail.As chip fabrication processes progress deep into the sub-micronlevel and Integrated Circuits (ICs) and Field Programmable GateArrays (FPGAs) can support larger and larger amounts of logic,system designers require increasingly high-level tools to keep up.Recently, industry has targeted C/C and variants as potentiallong-term replacements for Hardware Description Languages(HDLs) such as VHDL and Verilog currently employed fortoday’s hardware design. Also, as technologies increase indensity in both the fabricated and reconfigurable areas, powerconsumption becomes a progressively more important problem.While some work has been done in targeting C/C as an HDLand considering power-consumption in hardware synthesis,combining the two tasks creates a new challenge.This paper presents PACT HDL, a compiler targeting the Clanguage that produces synthesizable HDL usable for eitherFPGA designs or Application Specific ICs (ASICs) with aframework for both power and performance optimizations. PACTHDL supports arbitrary target architectures and allows for bothpower and performance optimizations at the C level or at an HDLlevel. The compiler uses a back-end to generate synthesizableRegister Transfer Level (RTL) HDL codes, such as VHDL andVerilog, current industry standards. It can be easily extended tosupport new HDL codes as they are developed.*Categories and Subject Descriptors1.1 PACTB.5.2 [Register Transfer Level Implementation]: Design Aids –automated synthesis, hardware description languages, andoptimizationPACT HDL is part of the PACT (Power Aware Architecture andCompilation Techniques) project. The objective of PACT is todevelop power-aware architectural techniques and associatedcompiler and CAD tool support that will take applications writtenin C and generate efficient code that runs on power-awaresystems. The end goal is to generate power savings at all levels inthe design process toward an overall high aggregate powersavings. This is the first in a series of papers on the PACTcompiler project. The compiler framework and introductoryoptimizations are presented. Later papers will focus on these andother optimizations in detail. The PACT compiler targets aSystem on a Chip (SoC) style architecture consisting ofreprogrammable components (FPGAs), application-specificcomponents (ASICs), and a general-purpose processor (ARM).This paper focuses on the method for generating the descriptionsGeneral TermsAlgorithms, DesignKeywordscompiler, HDL, VHDL, Verilog, FPGA, ASIC, SoC, synthesis,low-power, high-performance, FSM, pipelining, levelization, IPPermission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. To copyotherwise, or republish, to post on servers or to redistribute to lists,requires prior specific permission and/or a fee.CASES 2002, October 8-11, 2002, Grenoble, France.Copyright 2002 ACM 1-58113-575-0/02/0010 5.00.*188This research was supported by DARPA under contract F3361501-C-1631 and by NASA under contract 276685

the entire C/C language, including pointers, arrays, and higherlevel constructs [35].C ProgramDirectives andAutomationSome related work has been to target other high-level languagesfor hardware generation. Superlog is a language based on bothVerilog and C by Co-Design Automation, Inc [11]. The MATCHgroup at Northwestern University has built a synthesizable RTLVHDL compiler from the MATLAB programming language[7].Xilinx, Inc. targeted Java as an HDL for its Forge-J HDLcompiler[13].C Librarieson various TargetsSUIFHW / SWPartitionerC to RTLVHDL/VerilogSUIF to GCCGCC compiler forembeddedVHDL toFPGA SynthesisVHDL toASIC SynthesisObject code forStrongARMBinaries forFPGAsChip layouts(0.25 µm TSMC)As the proliferation of battery powered portable electronics hasincreased, so has the work on power-optimized hardware. Manyof these approaches are applicable toward automated poweroptimizing compilers. At UC-Berkeley, power optimization workhas been done in conjunction with the wireless research centerdealing at the CMOS level[10] and using computationaltransformations in high-level synthesis with HYPER-LP[9].Additional work on power-optimized synthesis has been done atPolytechnic University of Catalonia [27] and Princeton University[21][22].Figure 1.1. PACT Compiler Flowfor the hardware components of the SoC and describes someinitial power optimizations. PACT HDL integrates with a toplevel hardware/software partitioner and a power optimizinggeneral-purpose processor compiler to make up the larger PACTcompiler. PACT HDL is designed with signal and imageprocessing algorithms in mind. Often these sorts of problemswould be handed by application-specific hardwares in the SoCsetting. The flow of the PACT Compiler is illustrated in Figure1.1.In contrast to many of the C based synthesis tools, PACT HDLtargets unmodified ANSI C as its source language. While manyof these tools are also platform specific, PACT HDL is targetarchitecture independent. PACT HDL generates power-awareHDL designs as compared to performance and area metrics thatdominate many of these related tools. The main contribution ofPACT HDL is to develop a C to VHDL/Verilog compiler withpower optimizations for FPGAs and ASICs in arbitraryarchitectures.1.2 Related WorkRecently, there has been a lot of work in the use of the Cprogramming language and other high-level languages to generatesynthesizable HDL codes or hardware implementations.Galloway at the University of Toronto has developed theTransmogrifier C compiler. This compiler uses a subset of the Clanguage and targets a Xilinx 4000 series FPGA[18]. Micheli etal. have developed HardwareC, a C like language that containsmany HDL extensions.The Olympus Synthesis Systemsynthesizes digital circuit designs written in HardwareC[14]. TheEsterel-C Language (ECL) developed at Cadence BerkeleyLaboratories is an HDL and compilation suite based on the Clanguage[15]. CoWare, Inc. has developed the N2C layer forexisting languages, C in particular, by adding clocking and cycleinformation to allow hardware modeling[4]. CynApps, Inc. hasdeveloped a suite of tools based on macro and library extensionsfor C/C . These macros allow coding in C with an HDLstyle and the tools generate RTL HDL codes[12]. SystemC isanother C-like language developed by Synopsys to allow C-likeHDL coding that is particularly popular. The suite of toolsassociated with it can generate hardware directly[29]. AdelanteTechnologies (formerly Frontier Design) has a tool called A RTBuilder that takes a subset of C and generates VHDL[1]. Celoxicahas developed a compiler that takes a version of C called HandleC and generates VHDL for FPGAs[8] Maruyama and Hoshinohave developed a method for translating C loop structures into apipelined FPGA implementation[25].1.3 OutlineThe remainder of the paper is outlined as follows: Section 2describes the PACT HDL Compiler infrastructure. All stages ofthe compilation are discussed from the front-end C parsing to theback-end code generation. Implementation issues and thesuitability for optimizations at different phases are discussed.Section 2.5 explains the synthesis flow for both ASICs andFPGAs using the compiler’s output code. Specific optimizationsfor power and performance at different compiler levels arediscussed in Section 3. Section 4 presents some initial results aswell as ongoing work. Section 5 discusses some conclusions andSection 6 relates some future work. References are listed inSection 7.2. PACT HDLPACT HDL is a fully modularized three-stage C to HDLcompiler. In the first stage, the C code is parsed into a high-levelARCH f particular interest in the synthesizable C community is thehandling of pointers and other derived constructs. At Stanford,Séméria and De Micheli have done work to handle the problemby attempting to eliminate the loads and stores generated bypointers in C through special control flow[32]. C Level DesignInc. has developed the System Compiler that claims to handleCSUIFPower RCHPower &PerformanceOptimizationsVHDLASTHDLASTHDL2VHDLPACT HDL COMPILERFigure 2.1. PACT HDL Compiler Flow189VHDL

ProcessFSM StateLocalSymtabSymbol 1StateStateEntitySymbol 2ProcessFSM State Symbol 3:Symbol NStateStateState IDSignalsLocalSymtabGlobalSymtabSymbol 1Symbol 1Symbol 2Symbol 2Symbol 3:Symbol NSymbol 3:Symbol NStatement OneStatement Two:Statement N(If Statement)Next State AlternateFigure 2.3. HDL AST State Nodealso contains a local symbol table and a FSM node. The globalsymbol table may contain only VHDL-style signals so that theymay be globally visible across processes. The local symbol tablemay hold either VHDL signals or variables for the differentconcurrency properties. VHDL style signals in a local symboltable are treated as visible only locally even though they are infact visible globally. The FSM node describes the behavior of theC function through a list of one or more state nodes. The ASThierarchy is shown in Figure 2.2.Signals orVariablesFigure 2.2. HDL AST HierarchyC type Abstract Syntax Tree (AST). At this stage, both powerand performance optimizations may be executed. In general,these optimizations will not require specific information about anHDL representation or about the target architecture, such asprecision analysis, constant-propagation, or loop unrolling.During the second stage, the C AST is converted into a FiniteState Machine (FSM) style HDL AST. Target architecturespecific information is inserted into the AST in this phase. Again,power and performance optimizations can be executed. Ingeneral, these optimizations require specific information aboutclocks, cycles, or the target architecture, such as memorypipelining, and clock-gating. Finally, RTL code is generated inthe back-end phase. This phase is not designed for optimization;however, if language-specific issues arise they are handled in thisphase.The core HDL AST node is the state node. A state contains oneor more statements. Since the FSM requires explicit control flow,a default and alternate exit are defined. Normally, the default exitis taken. The alternate is only required when an if statement ispresent. In that case, then and else correspond to the default andalternate exit, respectively. For this reason, each state is limitedto one if statement, and the if statement can only be used forcontrol flow. Each state node also has a unique identifier withineach process. The state node is shown in Figure 2.3.The rest of the AST nodes are built out of generally wellunderstood types of structures. For simplicity there are only fivetypes of statements: assignments, ifs, sets, reads, and writes.Statements are built from unary, binary, and primary expressionsand operators. Most symbols are some sort of variable symbol,however, some other types exist such as label symbols.The PACT HDL compiler leverages the SUIF C CompilerVersion 1 from Stanford University [37] as its C front-end. SUIFwas chosen for its flexible AST representation that retains highand low level information simultaneously easing the developmentof AST passes and optimizations that operate at this level. SUIFis not designed to handle very large, complex codes such asoperating system kernels. This limitation is tolerable since theclasses of problems PACT HDL targets are computationallycomplex rather than algorithmically complex. The PACT HDLcompiler flow is shown in Figure 2.1.The HDL AST does not maintain direct facilities for retaininghigh level C structure information such as loops. If thisinformation is required it is stored in the associated HDL ASTnodes using annotations. The HDL AST is described in moredetail in Jones[19].2.2 SUIF to HDL Translation2.1 HDL ASTRather than directly translating the SUIF C like AST into aVHDL or Verilog-specific AST, an interim level of abstractionwas created. This approach is very different than the