HDL Coding Techniques - HIgh-Tech Consulting

3m ago
16 Views
0 Downloads
955.34 KB
102 Pages
Transcription

Chapter 4HDL Coding TechniquesIntroductionHardware Description Language (HDL) coding techniques let you: Describe the most common functionality found in digital logic circuits. Take advantage of the architectural features of Xilinx devices. Templates are available from the Vivado Integrated Design Environment (IDE). Toaccess the templates, in the Window Menu, select Language Templates.Coding examples are included in this chapter. Download the coding example files from:Coding Examples.Advantages of VHDL Enforces stricter rules, in particular strongly typed, less permissive and error-prone Initialization of RAM components in the HDL source code is easier (Verilog initial blocksare less convenient) Package support Custom types Enumerated types No reg versus wire confusionAdvantages of Verilog C-like syntax More compact code Block commenting No heavy component instantiation as in VHDLSynthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback67

Chapter 4: HDL Coding TechniquesAdvantages of SystemVerilog More compact code compared to Verilog Structures and enumerated types for better scalability Interfaces for higher level of abstraction Supported in Vivado synthesisFlip-Flops, Registers, and LatchesVivado synthesis recognizes Flip-Flops, Registers with the following control signals: Rising or falling-edge clocks Asynchronous Set/Reset Synchronous Set/Reset Clock EnableFlip-Flops, Registers and Latches are described with: sequential process (VHDL) always block (Verilog) always ff for flip-flops, always latch for Latches (SystemVerilog)The process or always block sensitivity list should list: The clock signal All asynchronous control signalsFlip-Flops and Registers Control SignalsFlip-Flops and Registers control signals include: Clocks Asynchronous and synchronous set and reset signals Clock enableSynthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback68

Chapter 4: HDL Coding TechniquesCoding Guidelines Do not asynchronously set or reset registers. Control set remapping becomes impossible. Sequential functionality in device resources such as block RAM components andDSP blocks can be set or reset synchronously only. If you use asynchronously set or reset registers, you cannot leverage deviceresources, or those resources are configured sub-optimally.Do not describe flip-flops with both a set and a reset. No Flip-flop primitives feature both a set and a reset, whether synchronous orasynchronous. Flip-flop primitives featuring both a set and a reset may adversely affect area andperformance. Avoid operational set/reset logic whenever possible. There may be other, lessexpensive, ways to achieve the desired effect, such as taking advantage of the circuitglobal reset by defining an initial content. Always describe the clock enable, set, and reset control inputs of flip-flop primitives asactive-High. If they are described as active-Low, the resulting inverter logic willpenalize circuit performance.Flip-Flops and Registers InferenceVivado synthesis infers four types of register primitives depending on how the HDL code iswritten: FDCE: D flip-flop with Clock Enable and Asynchronous Clear FDPE: D flip-flop with Clock Enable and Asynchronous Preset FDSE: D flip-flop with Clock Enable and Synchronous Set FDRE: D flip-flop with Clock Enable and Synchronous ResetFlip-Flops and Registers InitializationTo initialize the content of a Register at circuit power-up, specify a default value for thesignal during declaration.Flip-Flops and Registers Reporting Registers are inferred and reported during HDL synthesis. The number of Registers inferred during HDL synthesis might not precisely equal thenumber of Flip-Flop primitives in the Design Summary section.Synthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback69

Chapter 4: HDL Coding Techniques The number of Flip-Flop primitives depends on the following processes: Absorption of Registers into DSP blocks or block RAM components Register duplication Removal of constant or equivalent Flip-FlopsFlip-Flops and Registers Reporting -------------------------------------RTL Component ----------------------------------------Detailed RTL Component Info : ---Registers :8 BitRegisters : 1Report Cell Usage:----- ---- ---- Cell Count----- ---- ----3 FDCE 8----- ---- -----Flip-Flops and Registers Coding ExamplesThe following subsections provide VHDL and Verilog examples of coding for Flip-Flops andregisters. Download the coding example files from: Coding Examples.Register with Rising-Edge Coding Example (Verilog)Filename: registers 1.v//////////8-bit Register withRising-edge ClockActive-high Synchronous ClearActive-high Clock EnableFile: registers 1.vmodule registers 1(d in,ce,clk,clr,dout);input [7:0] d in;input ce;input clk;input clr;output [7:0] dout;reg [7:0] d reg;always @ (posedge 17UG901 (v2017.2)2017www.xilinx.comSend Feedback70

Chapter 4: HDL Coding Techniquesd reg 8'b0;else if(ce)d reg d in;endassign dout d reg;endmoduleFlip-Flop Registers with Rising-Edge Clock Coding Example (VHDL)Filename: registers 1.vhd------Flip-Flop withRising-edge ClockActive-high Synchronous ClearActive-high Clock EnableFile: registers 1.vhdlibrary IEEE;use IEEE.std logic 1164.all;entity registers 1 isport(clr, ce, clk : in std logic;d in: in std logic vector(7 downto 0);dout: out std logic vector(7 downto 0));end entity registers 1;architecture rtl of registers 1 isbeginprocess(clk) isbeginif rising edge(clk) thenif clr '1' thendout "00000000";elsif ce '1' thendout d in;end if;end if;end process;end architecture rtl;LatchesThe Vivado log file reports the type and size of recognized Latches.Inferred Latches are often the result of HDL coding mistakes, such as incomplete if or 7UG901 (v2017.2)2017www.xilinx.comSend Feedback71

Chapter 4: HDL Coding TechniquesVivado synthesis issues a warning for the instance shown in the following reportingexample. This warning lets you verify that the inferred Latch functionality was intended.Latches Reporting Example *Vivado.log* WARNING: [Synth 8-327] inferring latch for variable 'Q reg' ReportCell Usage:----- ---- ---- Cell Count----- ---- ----2 LD 1----- ---- ---- Latch With Positive Gate and Asynchronous Reset Coding Example (Verilog)Filename: latches.v// Latch with Positive Gate and Asynchronous Reset// File: latches.vmodule latches (input G,input D,input CLR,output reg Q);always @ *beginif(CLR)Q 0;else if(G)Q D;endendmoduleLatch With Positive Gate and Asynchronous Reset Coding Example (VHDL)Filename: latches.vhd-- Latch with Positive Gate and Asynchronous Reset-- File: latches.vhdlibrary ieee;use ieee.std logic 1164.all;Synthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback72

Chapter 4: HDL Coding Techniquesentity latches isport(G, D, CLR : in std logic;Q: out std logic);end latches;architecture archi of latches isbeginprocess(CLR, D, G)beginif (CLR '1') thenQ '0';elsif (G '1') thenQ D;end if;end process;end archi;\Tristates Tristate buffers are usually modeled by a signal or an if -else construct. This applies whether the buffer drives an internal bus, or an external bus on the boardon which the device resides The signal is assigned a high impedance value in one branch of the if-else.Download the coding example files from: Coding Examples.Synthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback73

Chapter 4: HDL Coding TechniquesTristate ImplementationInferred Tristate buffers are implemented with different device primitives when driving thefollowing: An external pin of the circuit (OBUFT) An Internal bus (BUFT): An inferred BUFT is converted automatically to logic realized in LUTs by Vivadosynthesis. When an internal bus inferring a BUFT is driving an output of the top module, theVivado synthesis infers an OBUF.Tristate Reporting ExampleTristate buffers are inferred and reported during synthesis. *Vivado log file* Report Cell Usage:----- ----- ---- Cell Count----- ----- ----1 OBUFT 1----- ----- ---- Tristate Description Using Concurrent Assignment Coding Example (Verilog)Filename: tristates 2.v// Tristate Description Using Concurrent Assignment// File: tristates 2.v//module tristates 2 (T, I, O);input T, I;output O;assign O ( T) ? I: UG901 (v2017.2)2017www.xilinx.comSend Feedback74

Chapter 4: HDL Coding TechniquesTristate Description Using Combinatorial Process Implemented with OBUFTCoding Example (VHDL)Filename: tristates 1.vhd-- Tristate Description Using Combinatorial Process-- Implemented with an OBUFT (IO buffer)-- File: tristates 1.vhd-library ieee;use ieee.std logic 1164.all;entity tristates 1 isport(T : in std logic;I : in std logic;O : out std logic);end tristates 1;architecture archi of tristates 1 isbeginprocess(I, T)beginif (T '0') thenO I;elseO 'Z';end if;end process;end archi;Tristate Description Using Combinatorial Always Block Coding Example(Verilog)Filename: tristates 1.v// Tristate Description Using Combinatorial Always Block// File: tristates 1.v//module tristates 1 (T, I, O);input T, I;output O;regO;always @(T or I)beginif ( T)O I;elseO 017UG901 (v2017.2)2017www.xilinx.comSend Feedback75

Chapter 4: HDL Coding TechniquesShift RegistersA Shift Register is a chain of Flip-Flops allowing propagation of data across a fixed (static)number of latency stages. In contrast, in Dynamic Shift Registers, the length of thepropagation chain varies dynamically during circuit operation.Download the coding example files from: Coding Examples.Static Shift Register ElementsA static Shift Register usually involves: A clock An optional clock enable A serial data input A serial data outputShift Registers SRL-Based ImplementationVivado synthesis implements inferred Shift Registers on SRL-type resources such as: SRL16E SRLC32EDepending on the length of the Shift Register, Vivado synthesis does one of the following: Implements it on a single SRL-type primitive Takes advantage of the cascading capability of SRLC-type primitives Attempts to take advantage of this cascading capability if the rest of the design usessome intermediate positions of the Shift RegisterShift Registers Coding ExamplesThe following subsections provide VHDL and Verilog coding examples for shift 1 (v2017.2)2017www.xilinx.comSend Feedback76

Chapter 4: HDL Coding Techniques32-Bit Shift Register Coding Example One (VHDL)This coding example uses the concatenation coding style.Filename: shift registers 0.vhd------32-bit Shift RegisterRising edge clockActive high clock enableConcatenation-based templateFile: shift registers 0.vhdlibrary ieee;use ieee.std logic 1164.all;entity shift registers 0 isgeneric(DEPTH : integer : 32);port(clk: in std logic;clken : in std logic;SI: in std logic;SO: out std logic);end shift registers 0;architecture archi of shift registers 0 issignal shreg : std logic vector(DEPTH - 1 downto 0);beginprocess(clk)beginif rising edge(clk) thenif clken '1' thenshreg shreg(DEPTH - 2 downto 0) & SI;end if;end if;end process;SO shreg(DEPTH - 1);end archi;32-Bit Shift Register Coding Example Two (VHDL)The same functionality can also be described as follows:Filename: shift registers 1.vhd//////////32-bit Shift RegisterRising edge clockActive high clock enableFor-loop based templateFile: shift registers 1.vmodule shift registers 1 (clk, clken, SI, SO);parameter WIDTH 32;input clk, clken, SI;output SO;Synthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback77

Chapter 4: HDL Coding Techniquesreg [WIDTH-1:0] shreg;integer i;always @(posedge clk)beginif (clken)beginfor (i 0; i WIDTH-1; i i 1)shreg[i 1] shreg[i];shreg[0] SI;endendassign SO shreg[WIDTH-1];endmodule8-Bit Shift Register Coding Example One (Verilog)This coding example uses a concatenation to describe the Register chain.Filename: shift registers 0.v//////////8-bit Shift RegisterRising edge clockActive high clock enableConcatenation-based templateFile: shift registers 0.vmodule shift registers 0 (clk, clken, SI, SO);parameter WIDTH 32;input clk, clken, SI;output SO;reg [WIDTH-1:0] shreg;always @(posedge clk)beginif (clken)shreg {shreg[WIDTH-2:0], SI};endassign SO shreg[WIDTH-1];endmodule32-Bit Shift Register Coding Example Two (Verilog)Filename: shift registers 1.v//////////32-bit Shift RegisterRising edge clockActive high clock enableFor-loop based templateFile: shift registers 1.vmodule shift registers 1 (clk, clken, SI, SO);Synthesis(v2017.1)JuneApril7,19,2017UG901 (v2017.2)2017www.xilinx.comSend Feedback78

Chapter 4: HDL Coding Techniquesparameter WIDTH 32;input clk, clken, SI;output SO;reg [WIDTH-1:0] shreg;integer i;always @(posedge clk)beginif (clken)beginfor (i 0; i WIDTH-1; i i 1)shreg[i 1] shreg[i];shreg[0] SI;endendassign SO shreg[WIDTH-1];endmoduleSRL Based Shift Registers ReportingReport Cell Usage:----- ------- ---- Cell Count----- ------- ----1 SRLC32E 1Dynamic Shift RegistersA Dynamic Shift register is a Shift register the length of which can vary dynamically duringcircuit operation.A Dynamic Shift register can be s