CHAPTER 5 A Closer Look At Instruction Set Architectures

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CHAPTER 5A Closer Look at Instruction Set Architectures5.1 Introduction 2935.2 Instruction Formats 2935.2.1 Design Decisions for Instruction Sets 2945.2.2 Little versus Big Endian 2955.2.3 Internal Storage in the CPU: Stacks versus Registers 2985.2.4 Number of Operands and Instruction Length 2995.2.5 Expanding Opcodes 3055.3 Instruction Types 3095.3.1 Data Movement 3095.3.2 Arithmetic Operations 3095.3.3 Boolean Logic Instructions 3105.3.4 Bit Manipulation Instructions 3105.3.5 Input/Output Instructions 3115.3.6 Instructions for Transfer of Control 3115.3.7 Special Purpose Instructions 3115.3.8 Instruction Set Orthogonality 3115.4 Addressing 3125.4.1 Data Types 3125.4.2 Address Modes 3135.5 Instruction-Level Pipelining 3165.6 Real-World Examples of ISAs 3215.6.1 Intel 3215.6.2 MIPS 3225.6.3 Java Virtual Machine 3235.6.4 ARM 327Chapter Summary 329CMPS375 Class Notes (Chap05)Page 1 / 17by Kuo-pao Yang

5.1 Introduction 293 In this chapter, we expand on the topics presented in the last chapter, the objectivebeing to provide you with a more detailed look at machine instruction sets.Employers frequently prefer to hire people with assembly language backgrounds notbecause they need an assembly language programmer, but because they needsomeone who can understand computer architecture to write more efficient andmore effective programs.We look at different instruction formats and operand types, and how instructionsaccess data in memory.We will see that the variations in instruction sets are integral in different computerarchitectures.Understanding how instruction sets are designed and how they function can help youunderstand the more intricate details of the architecture of the machine itself.5.2 Instruction Formats 293 MARIE had an instruction length of 16 bits and could have, at most 1 operand.Instruction sets are differentiated by the following:o Operand storage in the CPU (data can be stored in a stack structure or in register)o Number of explicit operands per instruction (zero, one, two, three being the mostcommon)o Operand location (instructions can be classified as register-to-register, register-tomemory or memory-to-memory, which simply refer to the combination ofoperands allowed per instruction)o Types of operations (including not only types of operations but also whichinstructions can access memory and which cannot)o Type and size of operands (operands can be addresses, numbers, or evencharacters)5.2.1 Design Decisions for Instruction Sets 294 Instruction set architectures are measured according to:o The amount of space a program requireso The complexity of the instruction set, in terms of the amount of decodingnecessary to execute an instruction, and the complexity of the tasks performed bythe instructionso The length of the instructionso The total number of instructionsIn designing an instruction set, consideration is given to:o Short instructions are typically better because they take up less space in memoryand can be fetched quickly. However, this limits the number of instructions,because there must be enough bits in the instruction to specify the number ofinstructions we need.o Instructions of a fixed length are easier to decode but waste space.CMPS375 Class Notes (Chap05)Page 2 / 17by Kuo-pao Yang

o Memory organization affects instruction format. Byte-addressable memorymeans every byte has a unique address even though words are longer then 1 byte.o A fixed length instruction does not necessarily imply a fixed number of operands.o There are many different types of addressing modes.o If words consist of multiple bytes, in what order should these bytes be stored ona byte-addressable machine? (Little Endian versus Big Endian)o How many registers should the architecture contain and how should theseregister be organized?5.2.2 Little versus Big Endian 295 The term endian refers to a computer architecture’s “byte order,” or the way thecomputer stores the bytes of a multiple-byte data element.Most UNIX machines are big endian, whereas most PCs are little endian machines.Most newer RISC architectures are also big endian.If we have a two-byte integer, the integer may be stored so that the least significantbyte is followed by the most significant byte or vice versa.o In little endian machines, the least significant byte is followed by the mostsignificant byte.o Big endian machines store the most significant byte first (at the lower address).FIGURE 5.1 The Hex Value 12345678 Stored in Both Big and Little Endian Format Big endian:o Is more natural.o The sign of the number can be determined by looking at the byte at address offset0.o Strings and integers are stored in the same order.Little endian:o Makes it easier to place values on non-word boundaries.o Conversion from a 16-bit integer address to a 32-bit integer address does notrequire any arithmetic.Computer networks are big endian, which means that when little endian computersare going to pass integers over the network, they need to convert them to networkbyte order.Any program that writes data to or reads data from a file must be aware of the byteordering on the particular machine.o Windows BMP graphics: little endiano Adobe Photoshop: big endiano GIF: little endiano JPEG: big endiano MacPaint: Big endianCMPS375 Class Notes (Chap05)Page 3 / 17by Kuo-pao Yang

ooooPC Paintbrush: little endianRTF by Microsoft: little endianSun raster files: big endianMS WAV, AVI, TIFF, XWD (X windows Dup): support both, typically byencoding an identifier into the file5.2.3 Internal Storage in the CPU: Stacks versus Registers 298 The next consideration for architecture design concerns how the CPU will store data.We have three choices:1. A stack architecture2. An accumulator architecture3. A general purpose register (GPR) architecture.In choosing one over the other, the tradeoffs are simplicity (and cost) of hardwaredesign with execution speed and ease of use.In a stack architecture, instructions and operands are implicitly taken from the stack.o A stack cannot be accessed randomly, which makes it difficult to generateefficient code.In an accumulator architecture such as MARIE, one operand is implicitly in theaccumulator, minimize the internal complexity of the machine and allow for veryshort instructions.o One operand is in memory, creating lots of bus traffic.In a general purpose register (GPR) architecture, registers can be used instead ofmemory.o Faster than accumulator architecture.o Efficient implementation for compilers.o Results in longer instructions, causing longer fetch and decode times.Most systems today are GPR systems.The general-purpose architecture can be broken into three classifications, dependingon where the operands are located:o Memory-memory where two or three operands may be in memory.o Register-memory where at least one operand must be in a register.o Load-store where no operands may be in memory (require data to be moved intoregisters before any operations on those data are performed).Intel and Motolrola are examples of register-memory architecturesDigital Equipment’s VAX architecture allows memory-memory operations.SPARC, MIPS, ALPHA, and PowerPC are all load-store machines.CMPS375 Class Notes (Chap05)Page 4 / 17by Kuo-pao Yang

5.2.4 Number of Operands and Instruction Length 299 The number of operands and the number of available registers has a direct affect oninstruction length.The traditional method for describing a computer architecture is to specify themaximum number of operands, or addresses, contained in each instruction.MARIE uses a fixed length instruction with a 4-bit opcode and a 12-bit operand.Instructions can be formatted in two ways:o Fixed length: Wastes space but is fast and results in better performance wheninstruction-level pipelining is used.o Variable length: More complex to decode but saves storage space.The most common instruction formats include zero, one, two, or three operands.Arithmetic and logic operations typically have two operands, but can be executedwith one operand (as we saw in MARIE), if the accumulator is implicit.In MARIE, the maximum was one, although some instructions had no operands(Halt and Skipcond).Machine instructions that have no operands must use a stack.Stack machines use one - and zero-operand instructions.In architectures based on stacks, most instructions consist of opecode only.Stack architecture need a push instruction and a pop instruction, each of which isallowed one operand (Push X, and Pop X). PUSH and POP operations involve onlythe stack’s top element.LOAD and STORE instructions require a single memory address operand.Other instructions use operands from the stack implicitly.Binary instructions (e.g., ADD, MULT) use the top two items on the stack.Stack architectures require us to think about arithmetic expressions a little differently.o We are accustomed to writing expressions using infix notation, such as:Z X Y.Stack arithmetic requires that we use postfix notation: Z XY .o This is also called reverse Polish notation.The principal advantage of postfix notation is that parentheses are not used.EXAMPLE 5.7 Suppose we wish to evaluate the following expression:Z (X * Y) (W * U)o Typically, when three operands are allowed one operand must be a register andthe first operand is normally the destination. The infix expression:Z (X * Y) (W * U)might look like this:MULT R1, X, YMULT R2, W, UADD Z,R2, R1o In a two-address ISA, normally one address specifies a register. The otheroperand could be either a register or a memory address. The infix expression:Z (X * Y) (W * U)might look like this:CMPS375 Class Notes (Chap05)Page 5 / 17by Kuo-pao Yang

LOADMULTLOADMULTADDSTORER1,R1,R2,R2,R1,Z,XYWUR2R1o In a one-address ISA (like MARIE), we must assume a register (normally theaccumulator) is implied as the destination. The infix expression,Z (X * Y) (W * U)looks like this:LOAD XMULT YSTORE TEMPLOAD WMULT UADD TEMPSTORE Zo In a stack ISA, the infix expression,Z (X * Y) (W * U),becomes in postfix notation.Z XY*WU* might look like this:PUSH XPUSH YMULTPUSH WPUSH UMULTADDPUSH Z We have seen how instruction length is affected by the number of operands supportedby the ISA.In any instruction set, not all instructions require the same number of operands.Operations that require no operands, such as HALT, necessarily waste some spacewhen fixed-length instructions are used.CMPS375 Class Notes (Chap05)Page 6 / 17by Kuo-pao Yang

5.2.5 Expanding Opcodes 305 Expanding opcodes represent a compromise between the need for a rich set opcodeand desire to have short opcode.One way to recover some of this space is to use expanding opcodes.A system has 16 registers and 4K of memory.We need 4 bits to access one of the registers. We also need 12 bits for a memoryaddress.If the system is to have 16-bit instructions, we have two choices for our instructions:FIGURE 5.2 Two Possibilities for a 16-Bit Instruction Format If we allow the length of the opcode to vary, we could create a very rich instructionset.EXAMPLE 5.8 Suppose we wish to encode the following instructions:- 15 instructions with 3 addresses- 14 instructions with 2 addresses- 31 instructions with 1 address- 16 instructions with 0 addresseso Can we encode this instruction set in 16 bits? The answer is yes, as long as we useexpanding opcodes. The encoding is as follows:CMPS375 Class Notes (Chap05)Page 7 / 17by Kuo-pao Yang

EXAMPLE 5.11 Given 8-bit instructions, is it possible to allow the following to beencoded?- 3 instructions with two 3-bit operands.- 2 instructions with one 4-bit operand.- 4 instructions with one 3-bit operand.o First, we must determine if the encoding is possible.- 323 192 bit patterns for the 3-bit operands- 224 32 bit patterns for the 4-bit operands- 423 32 bit patterns for the 3-bit operands.o If we sum the required number of bit patterns, we get 192 32 32 256. 8 bitin the instruction means a total of 28 256 bit patterns, so we have an exact match(which means the encoding is possible, but every bit patter will be used in cratingit.)o The encoding we can use is as follows:CMPS375 Class Notes (Chap05)Page 8 / 17by Kuo-pao Yang

5.3 Instruction Types 309 Instructions fall into several broad categories that you should be familiar with:o Data movement (ex. move, load, store)o Arithmetic (ex. add, subtract, multiply, divide)o Boolean (and, or, not, xor)o Bit manipulation (shift and rotate)o I/Oo Control transfer (ex. branch, skip, procedure call, returns, and programtermination)o Special purpose (ex. String processing, protection, flag control, cachemanagement)CMPS375 Class Notes (Chap05)Page 9 / 17by Kuo-pao Yang

5.4 Addressing 312 We now present the two most important of these addressing issues:o Types of data that can be addressed ando The various addressing modes.5.4.1 Data Types 312 Numeric data consists of integers and floating point values.Nonnumeric data types consist of strings, Booleans, and pointers.o String instructions typically include operations such as copy, move, search, ormodify.o Boolean operations include AND, OR, XOR, and NOT.o Pointers are actually addresses in memory.5.4.2 Address Modes 313 Addressing modes allow us to specify where the instruction operands are located.An addressing mode can specify a constant, a register, or a memory location.The actual location of an operand is its effective address.Immediate addressing is where the data to be operated on is part of the instruction.Direct addressing is where the address of the data is directly given in the instruction.Register addressing is where the data is located in a register.Indirect addressing gives the address of the address of the data in the instruction.Register indirect addressing uses a register to store the address of the address of thedata.Indexed addressing uses a register (implicitly or explicitly) as an offset (ordisplacement), which is added to the address in the