Xilinx XAPP1113 Designing Efficient Digital Up And Down .

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Application Note: Virtex-5 FamilyDesigning Efficient Digital Up and DownConverters for Narrowband SystemsRXAPP1113 (v1.0) November 21, 2008SummaryAuthor: Stephen Creaney and Igor KostarnovDigital Up Converters (DUC) and Digital Down Converters (DDC) are key components of RFsystems in communications, sensing, and imaging. This application note demonstrates howefficient DUC/DDC implementations can be created by leveraging Xilinx DSP tools and IPportfolio for increased productivity and reduced development time. While previous applicationnotes [Ref 1] have provided examples of DUC and DDC implementation in widebandcommunications systems, this document concentrates on narrowband systems and thebuilding block components available to meet the particular requirements of such designs.Step-by-step guidance is provided on how to perform simulation of narrowband DUC/DDCsystems in MATLAB , how to map functions onto building blocks and IP cores for Xilinx FPGAs in System Generator software, and how to verify the implementation against thesimulation model. Two examples are provided: a multi-carrier GSM system (both DUC andDDC) and a multi-channel MRI receiver (DDC only). The examples provide a guide andtemplate for implementation of customer-specific solutions and, in many cases, may be readilyadapted to customers’ own application systems. Advantages and limitations of the approachesand methods employed are identified such that the reader can consider these in their ownsystem context.IntroductionIn terms of signal processing, narrowband systems are generally characterized by the fact thatthe bandwidth of the signal of interest is significantly less than the sampled bandwidth; that is,a narrow band of frequencies must be selected and filtered out from a much wider spectralwindow in which the signal might occur. This means that large sample rate changes (in thehundreds or even thousands) must be undertaken to efficiently process the signal for eithertransmission or reception. Examples of such systems include: communications systems, whereseveral narrow channels must be recovered from a wider transmission band, or medicalimaging systems, such as MRI, where the detected waveforms occur in a narrow range offrequencies at varying points within a wider spectrum, as well as many other systems that fallwithin this grouping.[Ref 1] deals with wideband systems, providing guidance on how to select an appropriatecascaded FIR structure to meet the sample rate change requirements of wireless basestations. When the desired sample rate change is 32 or more, it is advisable to consider the useof CIC filters. CIC filters are an alternative class of filters to FIR filters, and they are well-suitedto large sample rate changes, as they can be implemented efficiently in digital circuits. They areoften used in conjunction with small Finite Impulse Response (FIR) filters to implement the filterchain of up- and down-converters in narrowband systems. While such converters have beenimplemented often for many years in both Application Specific Standard Products (ASSPs) andFPGAs, these have generally provided only single-channel solutions, or multiple instancesthereof. The latest high-density FPGA families with advanced architectures, in combination withefficient IP cores and effective design tools, provide the capability to handle many channelssimultaneously. This application note demonstrates how to implement such designs.Highlights: DUC and DDC design files for 4-carrier GSM, targeting Virtex -5 FPGAs 2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the propertyof their respective owners.XAPP1113 (v1.0) November 21, 2008www.xilinx.com1

RIntroduction DDC design files for multi-channel MRI, targeting both Virtex-5 and Spartan -DSPFPGAs Designed using class-leading Xilinx DSP IP portfolio Design flow for System Generator software for both designs Automatic scripted generation of implementation schematics based on system parametersfor the MRI design.System RequirementsThis application note was designed using MATLAB version 7.3.0 (R2006b) and the unifiedrelease of the Xilinx ISE and DSP tools (System Generator) version 10.1.Additional ReadingIt is recommended that the reader be familiar with data sheets for the Xilinx CascadedIntegrator Comb (CIC) Compiler [Ref 2], Direct Digital Synthesizer (DDS) Compiler [Ref 3], andFinite Impulse Response (FIR) Compiler [Ref 4] IP cores.A reasonable level of familiarity with Xilinx tools, in general, and System Generator software, inparticular, is assumed. Further information can be found in the software manuals [Ref 5]provided on the Xilinx website.Acronyms and AbbreviationsTable 1: Acronyms and Abbreviations3GPP3rd Generation Partnership ProjectADCAnalog-to-Digital ConverterAGCAutomatic Gain CorrectionASICApplication Specific Integrated CircuitASSPApplication Specific Standard ProductBlock RAMBlock Random Access Memory (Xilinx device resource)BSBase StationBTBandwidth-TimeBTSBase Transceiver StationCapExCapital ExpenditureCFRCrest Factor ReductionCICCascaded Integrator CombCFIRCompensation Finite Impulse Response FilterDACDigital-to-Analog ConverterdBDecibelDDCDigital Down ConverterDDSDirect Digital SynthesizerDFEDigital Front EndDPDDigital Pre-DistortionDSPDigital Signal Processing/ProcessorDUCDigital Up ConverterEDGEEnhanced Data rates for GSM EvolutionEDGE2 or e-EDGEEvolved EDGEFPGAField Programmable Gate ArrayFIDFree-Induction DecayFIRFinite Impulse ResponseXAPP1113 (v1.0) November 21, 2008www.xilinx.com2

RIntroductionTable 1: Acronyms and Abbreviations (Cont’d)GMSKGaussian Minimum Shift KeyingGSMGlobal System for Mobile Communication, originated from Groupe Spécial MobileGUIGraphical User InterfaceHDLHardware Description LanguageHORHardware Over-sampling RateIFIntermediate FrequencyIMDInter-Modulation DistortionISIInter-Symbol InterferencekbaudKilo-baud (1,000 symbols per second)kspsKilo-samples per second (1,000 samples per second)LSBLeast Significant Bit(s)LPFLow Pass FilterLUTLook-Up TableMACMultiply-AccumulateMRIMagnetic Resonance ImagingMSBMost Significant Bit(s)MSKMinimum Shift KeyingMspsMega-samples per second (1,000,000 samples per second)NCONumerically Controlled OscillatorOpExOperation ExpendituresPAPower AmplifierPAPRPeak-to-Average Power RatioPARPlace and RoutePFIRPulse-Shaping Finite Impulse Response (Filter)PSDPower Spectral DensityRMSRoot Mean SquareRRCRoot-Raised CosineRRHRemote Radio HeadSFDRSpurious-Free Dynamic RangeSNRSignal-to-Noise RatioTDDMTime Division De-MultiplexTDMTime Division MultiplexXSTXilinx Synthesis TechnologyXAPP1113 (v1.0) November 21, 2008www.xilinx.com3

RContentsContentsXAPP1113 (v1.0) November 21, 2008Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Up Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Down Converters (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Building Blocks for Narrowband DUC/DDC Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mixers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Direct Digital Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Finite Impulse Response Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CIC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Critical Design Parameters for DUC/DDC Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Total Rate Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Number of Carriers (or Subcarriers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Number of Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Supported Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Application Example: Multi-Carrier GSM (MC-GSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Up-Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Modeling and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DUC Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Limitations of CIC-based DUC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Down-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DDC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DDC Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DDC Modeling and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DDC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DDC Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DDC Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Limitations of CIC-Based DDC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Application Example: Multi-Channel MRI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Down-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Architectural Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Frequency